There exist a variety of schemes for message passing. The term "message passing" usually refers to an exchange of requests, responses and data between different computer systems. The requests and responses are queued up in each computer system, and there do exist arbitration means and routing means which forward the requests and responses to other computer systems.
One method for handling data exchange between different computer systems is to connect all the computer systems to one central system having a central memory. This central computer system, to which all the other computer systems are attached, is referred to as a "Coupling Facility". Message passing between different attached computer systems takes place by writing to and reading from said central system's memory. To each shared data structure in the memory of the coupling facility, different access keys and locks may be assigned, in a way that only a subset of the peripheral computer systems is allowed to perform read- and/or write-accesses to said data structures.
Such a solution is described in U.S. Pat. No. 5,561,809 "Communicating messages between processors and a coupling facility", to M. D. Swanson, B. B. Moore, J. A. Williams, J. F. Isenberg, A. A. Helffrich, D. A. Elko, and J. M. Nick. Here, data messages and responses are passed between the main storage of the respective computer system and the "structured external storage device" of the coupling facility by sub-channel means. In order to provide an arbitration mechanism, a completion vector exists having a bit which is set to its first condition when a message operation is started, and which is reset to its second condition when said message operation is completed. The state of said completion vector is polled periodically by the computer system that has started a message operation, in order to determine whether said message operation has completed.
The messages are to be passed from a first computer system to a second computer system via the coupling facility's central memory. The first computer system has to write its message to the central memory, and the second computer system has to fetch it from there. Therefore, the latency for message passing is high, because sequential write- and read-access to the coupling facility's central memory is necessary. Furtheron such a solution only makes sense for a multitude of computer systems being coupled to one central system. A coupling facility with only one or two attached computer systems does not make sense.
In order to couple computer systems, it has been proposed that one computer system may access the memory of its peer computer systems. The access to a "foreign" system's memory is forwarded to said memory via a so-called NUMA switch (Non-Uniform Memory Access). This means that each computer system can, with a low latency, access its own memory, and it can, with a somewhat higher latency, access the memories of its peer computer systems. Both read- and write-accesses to foreign memories are permitted. In order to take care of data integrity, it is necessary to keep track of the different intersystem accesses. This is done by assigning a directory to the NUMA-switch in which the status of all datalines in the different systems' memories is recorded. This shows one disadvantage of such a solution: A rather high amount of extra hardware is required, and complex routines have to be installed in order to preserve data integrity. By granting write authority for the own system's memory to other computer systems, the danger of hazards is increased.
Another method for passing messages between computer systems that is known from the prior art is to couple said computer systems by attaching a switch to both the I/O interface of the first and the I/O interface of the second computer system. In the IBM S/390 multiprocessor systems, the so-called "channel" connects I/O devices such as DASDs to the computer system's I/O adapters. The term "channel" refers both to the fiber link that connects the I/O devices to the computer system and to the transfer protocol employed on said fiber link. The channel is capable of serially transmitting 200 MBit of data per second. Per S/390 computer system, there may exist up to 256 channels.
It is possible to couple a computer system 1 with a computer system 2 by attaching one of the channels of computer system 1 and one of the channels of computer system 2 to a common channel switch. Thus, computer system 1 may access the I/O devices that are attached to computer system 2, and vice versa. Any of the computer systems can thus access any I/O device, no matter to which computer system said I/O device is attached. But besides addressing remote I/O devices, it is also possible, with said channel switch, to access the memory of any other computer system, and to perform remote read- and/or write-accesses to the other computer system's memory. Let us consider the case that computer system 1 has to pass a message to computer system 2. Said message has to be forwarded, via the I/O adapter of computer system 1, via a channel of computer system 1, via the channel switch, via a channel of computer system 2, and via the I/O adapter of computer system 2, to the memory of computer system 2. As this communication path is very long, message passing takes a long time and therefore, the main disadvantage of this method is its high latency. Another disadvantage is that each computer system is allowed to perform, via the channel switch, write-accesses to a "foreign" computer system, and therefore, hazards may occur. A faulty external write-access to the memory of one of the computer systems might destroy data integrity. Furtheron, message passing via a channel switch is only possible in case each of the computer systems is equipped with said channel links. There also exist less expensive solutions that allow to directly connect SCSI devices to the computer system's I/O adapters. For such "small" solutions, message passing via a channel switch is not possible anyway.
In U.S. Pat. No. 5,412,803 "High performance intersystem communication for data processing systems", to R. S. Capowsky, P. J. Brown, I. T. Fasano, T. A. Gregg, D. W. Westcott, N. G. Bartow and G. Salyer, a message passing scheme is proposed where dedicated buffers assigned to the node processors are used as mailboxes where the messages can be put by the connected node processors. Here, an originator buffer in a message originator element and a recipient buffer in a message recipient element are provided for message passing, whereby each of said originator buffers and each of said recipient buffers is composed of three logical areas, a request area, a response area, and a data area, and whereby a transmission path connects said originator buffer to said recipient buffer. A message request is transferred from the request area of the originator buffer to the request area of the recipient buffer and optionally, message data is transferred from the data area of the originator buffer to the data area of the connected recipient buffer. The message recipient element may respond by transferring a message response from the response area of the recipient buffer to the response area of the originator buffer, and, optionally, transfer message data from the data area of the recipient buffer to the data area of the originator buffer. Requests and responses have to queue up and are executed in sequence. A rather complicated message-time-out procedure is initiated each time a message is transmitted. A second disadvantage is that, in case there exist a multitude of communication paths between two computer systems, a large amount of buffers have to be provided. As each buffer is segmented into three logical areas, a lot of extra hardware is required, and therefore, this solution is rather expensive, and it uses a lot of valuable chip space. The problems that emerge when a "foreign" computer system performs a write access to the own system's memory are not received by this solution.